This invention relates to a DA converter (hereinafter referred to as a DAC), and particularly to a DAC which is suitable for a high speed converting operation.
A typical application of DACs is in a high definition display system, such as a computer terminal.
A high definition display system of the raster scan type having 1000 to 2000 scanning lines requires 100 to 500 MHz as its data renewal frequency.
A first drawback in such systems is that it is difficult to develop individual input bit data of a DAC in timed relationship at a speed as high as 500 MHz. A second drawback is in dispersion of transmission times of data transmitted to individual input bits of a DAC. For example, in a system wherein the data renewal frequency is 500 MHz, the period is 2 ns, and hence it is desirable that the dispersion of transmission times be less than a fraction of that. But it is very difficult to attain this because of dispersion of characteristics, such as data line length.
A third drawback resides in glitches (hair-like noises which may appear upon changing of data) and responsiveness of a DAC. Since glitches appear as noises on a display picture, they need be controlled to a low level to a degree. A DAC of the segment type is as a DA converting means which effectively controls glitches (refer, for example, to ISSCC, 1978, THPM142).
A theoretical representation of a DAC of the segment type is given in FIG. 9 which illustrates a construction of an 8 bit DAC wherein the means mentioned above is applied to the upper 3 bits. In particular, the DAC includes decoder drivers 901 for inputting the upper 3 bits, segment decoders 902, a group of flipflops 903, a first group 904 of switches connected to constant current sources, an input circuit 905 for inputting lower input bits, another group of flipflops 906, and another group 907 of switches connected to constant current sources. Thus, the upper n bits (n=3 in FIG. 9) to which glitches readily appear are converted into the decimal system by the segment decoders 902 to control a number determined by the decimal number of constant current outputting switches of the 2.sup.n -1 similar constant current sources disposed in the latter stage. According to the arrangement, even upon switching of the upper bits which will normally cause the highest glitches, that is, where n=3, upon switching between 011 and 100, the numbers of the constant current sources from which an output is taken change from 3 to 4, and hence there is only a change of 1 therebetween, resulting in glitches lower than that. Accordingly, glitches become lower than 1/2.sup.n -1 of the glitches which may appear in a conventional arrangement. However, in this arrangement, decoder output signals must necessarily be produced in timed relationship, and hence the flipflops F11 to F17 must be provided for the decoder outputs.
A fourth drawback resides in responsiveness of the DAC. Particularly, it is difficult, with the existing IC techniques to attain operation of a decoder or a latch at 500 MHz. If this should be possible, since it is necessary to reduce the impedance of a circuit system to attain a high speed, a large electric current is required, resulting in an increase of the power consumption, which makes the IC impractical as an IC.